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Started by Aidan, November 08, 2005, 09:17:52 PM

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Well, I'm a little confused as to just how the N64's DENC actually works in terms of signalling. This is what I think I've figured out so far. The video data pins are a little bit of an assumption, given that disconnecting them results in a change in the image that's consistant with disconnecting a bit. However, disconnecting pins 1 and 2 result in a signal that my display considers to be invalid. This might indicate that there's sync data being passed as well.

My theory at the moment is that the first 7 pins are actually all data. This data is clocked in four phases (hence the constant 12.5MHz signal on pin 9 vs the 50MHz shared clock). As there does not appear to be any seperate vsync/hsync, I'm assuming that something in one of the sets of data clocked in is used to indicate v and h sync.

pin 1 - d0?video data
pin 2 - d1?video data
pin 3 - d2?video data
pin 4 - d3?video data
pin 5 - d4?video data
pin 6 - d5?video data
pin 7 - d6?video data (MSB)
pin 8 - +3v
pin 9 - ? 12.5MHz signal
pin 10 - GND
pin 11 - shared clock with RCP (50MHz)
pin 12 - GND
pin 13 - GND
pin 14 - ?
pin 15 - ?
pin 16 - GND
pin 17 - +5v
pin 18 - C out
pin 19 - Y out
pin 20 - Composite out
pin 21 - ?
pin 22 - ?
pin 23 - ?
pin 24 - GND

Unfortunately, in this process I've managed to kill the DENC. However, I might see if I can validate my theories by trying to extract the four phases. Don't hold your breath on this though!
[ Not an authoritive source of information. ]


For fun, I just threw a DAC across the outputs, just to see what the output would be. The end result had poor sync, but did generate a grayscale image. That at least would tend to indicate that my guess at the bit ordering might be right!

Sorry for the darkness of the shot - the DAC wasn't optimised, so the signal level is significantly lower than it should be.
[ Not an authoritive source of information. ]


Oh, and the DAC "assembly" itself. Now you can see why it's rather suboptimal, but at least it proved the concept.

[ Not an authoritive source of information. ]


Let me get this straight.  You got a viewable image from the thing using a resistor DAC on a breadboard!?!  You sir are (explicative deleted) incredible! ^_^

I know a little lectronics myself but I would have never have worked up the guts to do what you have.  From what you have shown here the DENC chip mustn't be that complicated, Murphy's and Sod's Laws aside.

Anyway, I wish you luck on furthering this endevour!

PS.  I have a spare pal N64 myself and a 35MHz scope (hardly have aclue how to use, its been so long T_T), if there are any experiments that would help this cause you could suggest then by all means do so.  
Formerly 'butter_pat_head'


Viewable is an interesting term. :)

My guess is that the 12.5MHz clock starts a transfer cycle of four 'words', and one of those words contains some sync information. As there only appears to be 7 bits of data clocked, that would make 28bits total. The N64 is supposed to have 24bit colour, so that leaves four bits left over.

So, I guess four latches and a counter could do the job. As I'm going to have to replace the DENC now I've blown it up, I might have an oppertunity to find out.  
[ Not an authoritive source of information. ]


Bloody good work Aidan, keep it up!


I might run into some problems with the logic speeds. I've never really tried doing anything over a few MHz, so this might be a little more difficult than I expect. Still, the wolfsoft RGB mod looked like a PLD with three R/2R DACs...


You might want to get on forum and see if there's anyone left there who programmed scene demos etc that might be able to help you with how the N64 does its video.
I believe there are also a few tech docs available for download too, which might be of use to you.


The problem is that from software, you never see this side of the hardware. All you know is that it's there and it's working. It's the same way that you know there's a pair of DACs for sound, but you have no idea how the DSP actually sends the data to the DACs.
[ Not an authoritive source of information. ]


There are certain documents around, if you know where to look and who to ask. I've given you a starting point in my last post.


I'm the author of that Website.
Excuse me. I'm poor at Engilish. Please read the page using machine translation.

I think that all they are required.
The circuit is for outputting the signal of HuC6260 so that it may become 0.7 Vp-p in 75-ohm terminus.

NJM2267 is common video amplifier IC in Japan that it is easy to buy. It is IC which is easy to use NJM2267. However, a gain is unchangeable.

The RGB signal of HuC6260 is 4.2V to 5V, i.e., 0.8 Vp-p.
A signal is divided by resistance so that it may finally become 0.7 Vp-p. However, HuC6260 cannot drive the load.

Then, it once buffers using Emitter Follower.


Why not compare common pinout of VDC chip and DENC chip ? RCP has same pinout on two N64 model (DENC and VDC). RCP side of VDC has undoubtly common pinout, signals are the same.

Thos most hardly part of this mod is to find pinout of output signals of DENC chip.  


Simm's Club - French LAN Gaming (PC & Consoles) :


Test these pin on DENC chip : 21, 19 and 17 are RGB (maybe).


Simm's Club - French LAN Gaming (PC & Consoles) :


I don't quite get all the tech in here, but is this discussing the possibility of RGB modding a NUS-001 (EUR)
/NUS-CPU(P)-01/DENC-NUS N64???