For an array of ISA bus terminal


 Terminals of the ISA bus is made up as follows.
 This figure has been seen from the figure on the ISA bus connector.

	 	  + ----- +
	      Gnd | [] [] |-IOCHK
	 RESETDRV | [] [] | SD7
	     +5 V | [] [] | SD6
	     IRQ9 | [] [] | SD5
	      -5V | [] [] | SD4
	     DRQ2 | [] [] | SD3
	     -12V | [] [] | SD2
	     -OWS | [] [] | SD1
	    +12 V | [] [] | SD0
	      Gnd | [] [] | IOCHRDY
	   -SMEMW | [] [] | AEN
	   -SMEMR | [] [] | SA19
	     -IOW | [] [] | SA18
	     -IOR | [] [] | SA17
	   -DACK3 | [] [] | SA16
	     DRQ3 | [] [] | SA15
	   -DACK1 | [] [] | SA14
	     DRQ1 | [] [] | SA13
	 -REFRESH | [] [] | SA12
	      CLK | [] [] | SA11
	     IRQ7 | [] [] | SA10
	     IRQ6 | [] [] | SA9
	     IRQ5 | [] [] | SA8
	     IRQ4 | [] [] | SA7
	     IRQ3 | [] [] | SA6
	   -DACK2 | [] [] | SA5
	       TC | [] [] | SA4
	     BALE | [] [] | SA3
	     +5 V | [] [] | SA2
	      OSC | [] [] | SA1
	      Gnd | [] [] | SA0
		  + ----- +
		  + ----- +
	 -MEMCS16 | [] [] |-SBHE
	  -IOCS16 | [] [] | LA23
	    IRQ10 | [] [] | LA22
	    IRQ11 | [] [] | LA21
	    IRQ12 | [] [] | LA20
	    IRQ15 | [] [] | LA19
	    IRQ14 | [] [] | LA18
	   -DACK0 | [] [] | LA17
	     DRQ0 | [] [] |-MEMR
	   -DACK5 | [] [] |-MEMW	
	     DRQ5 | [] [] | SD8	
	   -DACK6 | [] [] | SD9
	     DRQ6 | [] [] | SD10
	   -DACK7 | [] [] | SD11
	     DRQ7 | [] [] | SD12
	     +5 V | [] [] | SD13
	  -MASTER | [] [] | SD14	
	      Gnd | [] [] | SD15
		  + ----- +


 Primary meaning of the signals is as follows.

LSB side of the space of 24-bit read / write signal SA0 ~ SA19 memory is memory
SMEMR signal is read / write read / write-IOR
MEMR signal is a signal of about 8MHz CLK
IOW of I / O
MEMW of memory
SMEMW 1MB of subordinate at 16-bit access

SBHE not be the case of I / O space is 20 bits must be full 16-bit decoding, in AEN DMA cycle 
indicates that the D8 ~ D15 is enabled, you will be H-REFRESH is the data bus SD0 ~ SD15 latching 
signal BALE is 7-bit address on the MSB side of the 24 bit memory space LA17 ~ LA23 during the cycle 
of the refresh of DRAM, will be L.  I / O slave

IOCS16 shows the bus request fast cycle is-0WS request 

IOCHRDY wait cycles indicates that the width is 16 bits for the CPU or the like that the memory 
slave is 16 bits wid

MEMCS16 the attention from the format Intel to interrupt on the rising edge of the H-MASTER-DACKn 
After receiving the transfer is allowed for the DMA transfer request is a request-DACKn DRQn DMA 
transfer indicates that this is a DMA TC is the last cycle, from IRQn L is a bus request signal 
By The-IOCHCK requests to L, is the signal OSC 14.31818MHz

RESETDRV signal is reset raises the non-maskable interrupt