OK so I traced all the connections on the PPU of my Rev. 4 NTSC USA Toaster NES and I got ;-
PPU ;-
pin 1 is R/W_, goes direct to pin 34 of 2A03 CPU and pin 21 of IC U1 (2K x 8 bits SRAM / Work RAM) and pin 14 of NES cart slot
pin 2 is D0, goes direct to pin 32 of Expansion port (CPU D0) and pin 49 of NES cart slot (PRG D0) and pin 3 of IC U7 and pin 3 of IC U8 and pin 28 of 2A03 CPU and pin 9 of IC WRAM (U1)
pin 3 is D1, goes direct to pin 31 of Expansion port (CPU D1) and pin 48 of NES cart slot (PRG D1) and pin 5 of IC U7 and pin 5 of IC U8 and pin 27 of 2A03 CPU and pin 10 of IC WRAM (U1)
pin 4 is D2, goes direct to pin 30 of Expansion port (CPU D2) and pin 47 of NES cart slot (PRG D2) and pin 9 of IC U7 and pin 9 of IC U8 and pin 26 of 2A03 CPU and pin 11 of IC WRAM (U1)
pin 5 is D3, goes direct to pin 29 of Expansion port (CPU D3) and pin 46 of NES cart slot (PRG D3) and pin 11 of IC U7 and pin 11 of IC U8 and pin 25 of 2A03 CPU and pin 13 of IC WRAM (U1)
pin 6 is D4, goes direct to pin 28 of Expansion port (CPU D4) and pin 45 of NES cart slot (PRG D4) and pin 13 of IC U7 and pin 13 of IC U8 and pin 24 of 2A03 CPU and pin 14 of IC WRAM (U1)
pin 7 is D5, goes direct to pin 27 of Expansion port (CPU D5) and pin 44 of NES cart slot (PRG D5) and pin 23 of 2A03 CPU and pin 15 of IC WRAM (U1)
pin 8 is D6, goes direct to pin 26 of Expansion port (CPU D6) and pin 43 of NES cart slot (PRG D6) and and pin 22 of 2A03 CPU and pin 16 of IC WRAM (U1)
pin 9 is D7, goes direct to pin 25 of Expansion port (CPU D7) and pin 42 of NES cart slot (PRG D7) and pin 21 of 2A03 CPU and pin 17 of IC WRAM (U1)
pin 10 is RS2, goes direct to pin 11 of NES cart slot (PRG A02) and pin 6 of 2A03 CPU and pin 6 of IC WRAM (U1)
pin 11 is RS1, goes direct to pin 12 of NES cart slot (PRG A01) and pin 5 of 2A03 CPU and pin 7 of IC WRAM (U1)
pin 12 is RS0, goes direct to pin 13 of NES cart slot (PRG A00) and pin 4 of 2A03 CPU and pin 8 of IC WRAM (U1)
pin 13 is DBE_, goes direct to pin 5 of U3 (74HC139P, Dual 2-to-4 line decoder/demultiplexer)
pin 14 is RED, goes to my Moosmann amp #1
pin 15 is BLUE, goes to my Moosmann amp #2
pin 16 is GREEN, goes to my Moosmann amp #3
pin 17 is MVGND and goes direct to Ground of NES PCB
pin 18 is CLK (PPUCLK), goes through C45 (51pF cap) and then though 220K ohms (R10) to the Base of Q2 and then through C43 (51pF cap) to ground, etc (i.e. from pin 18 of PPU then through the middle left section of "NES3" on the schematic)
pin 19 is NMI_, goes direct to pin 33 of 2A03 CPU and to pin 4 of Expansion port
pin 20 is Ground, goes direct to Ground on NES PCB
pin 21 is Composite Sync and goes direct to the Base of transistor Q1 (A397), the Collector is Grounded, and the Emitter goes direct to pin 21 of Expansion port. Also there is a direct connection from Emitter of Q1 to R2 (150 Ohms) (on the NES Schematic it is shown as 510 Ohms instead), then through R2 to VCC (pin 36 NES cart slot), and also a direct connection from Emitter of Q1 to FC2 (Ferrite Core/Choke), then through FC2, and then through C5 (330pF) to Ground of NES PCB. From Emitter of Q1 there is a direct connection to pin 1 of the 5 pins that goes into the RF box.
pin 22 is RST_, goes to pin 3 of 2A03 CPU, and pin 9 of U9, and pin 9 of U10
pin 23 is WE_ (CHR RAM WR_), goes direct to pin 56 of NES cart slot, and pin 21 of VRAM (U4). Electronix schematic is wrong (see below)
pin 24 is RD_ (CHR RAM RD_), goes direct to pin 21 NES cart slot, and pin 20 VRAM (U4). I added a 68pF cap from pin 24 PPU to Ground, to be the same as the PC10 (and Famicom!) schematic
pin 25 is PA13, goes direct to pin 65 of NES cart slot ("CHR A13" on the NES section of Ben Heck's NES / Famicom cart slot pinout) and to pin 5 of U9 and to the middle pin of RA2 (Resistor Array 2) then through 5.2K Ohms of RA2 to middle left pin of RA2 then to pin 36 of 2A03 CPU, also from middle pin of RA2 then through 9.7K Ohms of RA2 to far left hand pin of RA2 then to pin 35 of 2A03 CPU, also from middle pin of RA2 then through 7.6K Ohms of RA2 to middle right pin of RA2 then to pin 39 of 2A03 CPU, also from middle pin of RA2 then through 5.4K Ohms of RA2 to far right pin of RA2 then to pin 40 of 2A03 CPU and to VCC (pin 36 of NES cart slot)
pin 26 is PA12 (CHR A12), goes direct to pin 64 of NES cart slot
pin 27 is PA11 (CHR A11), goes direct to pin 62 of NES cart slot
pin 28 is PA10 (CHR A10), goes direct to pin 63 of NES cart slot
pin 29 is PA9 (CHR A09), goes direct to pin 61 of NES cart slot and pin 22 of VRAM (U4)
pin 30 is PA8 (CHR A08), goes direct to pin 60 of NES cart slot and pin 23 of VRAM (U4)
pin 31 is AD7 (CHR D7), goes direct to pin 18 of U2 (Toshiba TC74HC373P, Non-inverting Octal D-type Latch) then out of pin 19 of U2 (O8, output no.

then to pin 1 of VRAM (A7) and to CHR A07 i.e. pin 59 of NES cart slot. Also PPU pin 31 goes direct to AD7 and pin 17 of VRAM (U4) and CHR D7 i.e. pin 66 of NES cart slot
pin 32 is AD6 (CHR D6), goes direct to pin 3 of U2 (Toshiba TC74HC373P, Non-inverting Octal D-type Latch) then out of pin 2 of U2 (O1, output no. 1) then to pin 2 of VRAM (A6) and to CHR A06 i.e. pin 23 of NES cart slot. Also PPU pin 32 goes direct to AD6 i.e. pin 16 of VRAM (U4) and CHR D6 i.e. pin 67 of NES cart slot
pin 33 is AD5 (CHR D5), goes direct to pin 17 of U2 (Toshiba TC74HC373P, Non-inverting Octal i.e. Eight D-type Latches) then out of pin 16 of U2 (O7, output no. 7) then to pin 3 of VRAM (A5) and to CHR A05 i.e. pin 24 of NES cart slot. Also PPU pin 33 goes direct to AD5 i.e. pin 15 of VRAM (U4) and CHR D5 i.e. pin 68 of NES cart slot.
pin 34 is AD4 (CHR D4), goes direct to pin 4 of U2 (Toshiba TC74HC373P, Non-inverting Octal i.e. Eight D-type Latches) then 0ut of pin 5 of U2 (O2, output no. 2) then to pin 4 of VRAM (A4) and to CHR A04 i.e. pin 25 of NES cart slot. Also PPU pin 34 goes direct to AD4 i.e. pin 14 of VRAM (U4) and CHR D4 i.e. pin 69 of NES cart slot.
pin 35 is AD3 (CHR D3), goes direct to pin 14 of U2 (Toshiba TC74HC373P, Non-inverting Octal i.e. Eight D-type Latches) then out of pin 15 of U2 (O6, output no. 6) then to pin 5 of VRAM (A3) and to CHR A03 i.e. pin 26 of NES cart slot. Also PPU pin 35 goes direct to AD3 i.e. pin 13 of VRAM (U4) and CHR D3 i.e. pin 33 of NES cart slot.
pin 36 is AD2 (CHR D2), goes direct to pin 7 of U2 (Toshiba TC74HC373P, Non-inverting Octal i.e. Eight D-type Latches) then out of pin 6 of U2 (O3, output no. 3) then to pin 6 of VRAM (A2) and to CHR A02 i.e. pin 27 of NES cart slot. Also PPU pin 36 goes direct to AD2 i.e. pin 11 of VRAM (U4) and CHR D2 i.e. pin 32 of NES cart slot.
pin 37 is AD1 (CHR D1), goes direct to pin 13 of U2 (Toshiba TC74HC373P, Non-inverting Octal i.e Eight D-type Latches) then out of pin 12 of U2 (O5, output no. 5) then to pin 7 of VRAM (A1) and to CHR A01 i.e. pin 28 of NES cart slot. Also PPU pin 37 goes direct to AD1 i.e. pin 10 of VRAM (U4) and CHR D1 i.e. pin 31 of NES cart slot.
pin 38 is AD0 (CHR D0), goes direct to pin 8 of U2 (Toshiba TC74HC373P, Non-inverting Octal i.e. Eight D-type Latches) then out of pin 9 of U2 (O4, output no. 4) then to pin 8 of VRAM (A0) and to CHR A00 i.e. pin 29 of NES cart slot. Also PPU pin 38 goes direct to AD0 i.e. pin 9 of VRAM (U4) and CHR D0 i.e. pin 30 of NES cart slot.
pin 39 is ALE, goes direct to pin 11 of U2
pin 40 is VCC, goes direct to pin 36 of NES cart slot
My CPU is RP2A03E, batch 6K2 B1
IC U1 is a TMM2115BP-15 (2K x 8 bits SRAM 150ns/ Work RAM)
IC U2 is a Toshiba TC74HC373P (Non-inverting Octal D-type Latch with 3-State output, see
http://www.datasheetarchive.com/dl/Databooks-4/Book609-949.pdf )
IC U3 is a Toshiba TC74HC139P (Dual 2-to-4 line decoder/demultiplexer)
IC U4 is a TMM2115BP-15 (2K x 8 bits SRAM 150ns/ Video RAM)
IC U7 and U8 are both a Toshiba TC40H368P ("Hex bus drivers with 3-state outputs", or "Buffer Memory Address Registers", also called "Hex Buffers" and "Line Drivers", or "Drive Bus Lines"), the 368 version is the Inverted outputs version. D0 through D4 come out of U7's inverted outputs, and D0 through D4 also come out of U8's inverted outputs
U9 is a Toshiba TC74HCU0P (Hex Inverter)
U10 is the CIC Lockout Chip 3193A, batch 8644 A, copyright 1986 Nintendo, I have cut off pin 4 of this chip from the body of the chip
Q1 is an A937 transistor
Q2 is a C2021 transistor
NOTES:
1) My factory fitted PPU in this NES was RP2C02E-0, batch 6K3 43. I removed this and fitted a socket and added an RP2C03B, came from my PC10 PCB's. I used Moosmann's RGB mod.
2) In the above, a line after the label means INVERTED
3) The first 5 data bus lines i.e. D0 to D4 are all coming out of a TC40H368P hex inverter, but D5 to D7 are not!!!
4) As Salamander mentions, it would appear that either my NES Rev.4 does not follow this NES schematic, or that there is an error in the Electronix NES schematic, because DBE is shown as going through a 51pF cap and then to E of Q3, as well as through 510R to ground, and etc (through the middle left section of "NES3" on the schematic), whereas my NES DOES NOT. My NES follows the Famicom schematics instead, in that DBE (pin 13 of PPU) goes direct to pin 5 of U3, and it is instead PPU pin 18 (CLK) that goes direct to the C45 (51pF cap) and through the rest of the components aforementioned.
5) Also it shows on the Electronix NES schematic that a pin of U3 (not numbered!) connects to pin 18 of PPU (CLK). On my NES pin 18 of PPU (CLK) doesn't connect to ANY pin of my U3!
6) On the Electronix schematic, the C2021 transistor to the right of the 21.47727 Crystal (Q2) has it's Collector going through 510 Ohms to VCC. On my NES, this is instead a 1.2KOhms resistor, R11 (connecting to pin 36 of NES cart slot, i.e. VCC). Also the schematic shows Q3's Emitter going though 510R to ground, but my NES has it going through R12 (1.2KOhms) instead.
7) My NES has the 30pF (the one in parallel with the 18pF cap connected to the X'TAL) as a Variable capacitor (it's got an adjustment that you can do with a small cross point screwdriver), the NES schematic shows this as just a normal 30pF cap, so my NES follows the Famicom schematic in this case.
8 ) On the Electronix schematic, I don't know what the hell they are trying to show on "WR" pin of PPU, but it can't be pin 21 as shown, since 21 is Composite Video. They must mean WR = Write = Write Enable, which instead should be on PPU pin 23 (so it's a typo, should have been "23" and seeing as it's next to pin 24 I assumed they meant it to be in numerical order), should be going to 21 of VRAM (U4) (i.e. should connect two lines lower down!). Instead it's shown going to pin 19 of VRAM (VRAM CHR A10), and this doesn't even connect to the PPU! (note in the above that pin 28 is CHR A10 but is NOT the same as VRAM CHR A10, which goes to pin 22 of NES cart slot). There should NOT be a connection from pin 19 VRAM to PPU pin 23! Pins 26, 27, 28 of PPU (PA12, PA11, PA10) are not even shown on the PPU pinout!
9) Expansion port pin 21 is connected to Emitter of Q1 (A397) i.e. VIDEO (since Q1's base connects to pin 21 of PPU i.e. Composite Video, and Audio is on pin 22 of Expansion port, since it connects with very low resistance to pin 2 of the 5 pins where I am taking internal mono audio from for my stereo audio mod. So this is basically the reverse of the pinout on the NESDev Wiki for NES (Expansion port pinout webpage) where they have pin 21 Expansion port as audio and pin 22 as Video, i.e. NESDev has them swapped on that webpage of theirs. I have reported this on the NesDev forums, maybe a moderator will correct it.
10) On the Famicom schematic, it uses 2 resistors (R6 2.2K, R12 220R) instead of just the one (R2, 150R) on my NES, for the Composite Video section, in the part which goes from Emitter of Q1 to VCC. On the Famicom, the Video output is taken from between these two resistors. The "diagonal rectangle" immediately to the right of the 2SA937 transistor in the NES schematic is FC2. From Emitter of Q1 there is a direct connection to pin 1 of the 5 pins that goes into the RF box, and pin 2 is internal mono audio and pin 3 is VCC (none are ground, the RF casing itself is ground).
11) It seems that there is another mistake in the Electronic NES Schematic in that A0, A1, A2 are shown as PPU pins (not numbered!) and are infact instead CHR A12, CHR A11, CHR A10 respectively, PPU pins 26, 28, 27 on NES cart pins 64, 62, 63, and called PA12, PA10, PA11 in the Famicom schematics. AS well as this, if you compare NES and Famicom cart slots, Famicom has pins 53, 54, 55 as CHR A10, CHR A11, CHR A12, whereas NES has them on 62, 63, 64 and they are CHR A11, CHR A10, CHR A12 on the NES as the NES swaps the former 2 pins (CHR A10, CHR A11) around compared to the Famicom cart connector, but this latter part is true and not a mistake in the schematic.
12) PPU Pin 24 RD (CHR RAM RD) goes through 68pF to Ground on Famicom Schematic, just like on the PlayChoice 10. On my NES it didn't, so I added it when I did the NES RGB mod.
13) On the Electronix NES schematic, PPU pin 25 (PA13) is showing as connecting to pin 37 (CHR ROM OUTPUT ENABLE as it is labelled, but labelled as CLOCK on the NES DEV Wiki's 72 pin slot pinout) and going through C44 (220pF cap) to pin 29 of 2A03 CPU, and to the section on the middle left in Electronix NES schematic's "NES 3" section (clock components). This is another mistake as on my NES there is no electrical connection between PPU pin 25 and NES cart slot pin 37. Instead, pin 25 of PPU is connected to pin 65 of NES cart slot (CHR A13). The Famicom schematic shows a connection from PPU pin 25 to pin 12 of U7 (40H368) but on my NES PPU pin 25 does not connect to ANY pin on either U7 or U8 of my NES!
14) Pin 6 of U9 (TC74HCU04P, hex inverter) on my NES goes to pin 58 of NES cart slot (CHR A13 inverted, note that there are two CHR A13's on the NES cart slot, one is CHR A13 (pin 65) (connected to pin 25 of PPU), the second is this one (CHR A13 inverted). The Famicom also has CHR A13 inverted, on pin 49 of the Famicom cart slot. In a similar way to the NES, PPU pin 25 (CHR A13) goes direct to pin 12 of U7 (40H368, contains 2 inverters in the Famicom schematic) and gets inverted in U7 onto pin 11 of U7, then goes to pin 49. So U7 in Famicom is doing the job that U9 does in the Toaster NES, for CHR A13
15) Pin 40 of PPU (VCC) is not shown on the Electronix NES schematic of the PPU!
16) On my RGB NES I am instead using pin 21 of PPU as Composite Sync (same as PC10 of course) instead of Composite Video, but that's the only change from a normal Toaster NES for this PPU pin. I am still routing the Composite Sync through the RF box to amplify it, in exactly the same way that the Toaster NES does with it's Composite Video, I am using exactly the same circuit, then out to Composite Video pin on SCART, as my TV in RGB mode still uses Composite Video to get it's Sync signal from, as do most TV's apparently.
17) A few times whilst testing I noticed that there was more Ohms (e.g. 15!) than there should have been between a few pins on the 72 pin connector and the PCB, so I pulled it out a little and back in and the connection was then back to being good. Morale of the story, get a toploader !!
18) Two more important links for cross referencing the Famicom and NES schematics by the cart slot connections are ;-
http://wiki.nesdev.com/w/index.php/NES_expansion_port_pinout and
http://benheck.com/Downloads/NES_Famicom_Pinouts.pdfCheers,
Alistair G.